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January 11, 2011

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Comments

George Storm

Agreed that there will in principle always be multiple resonances, but fortunately there are design techniques that can minimise the heights of the peaks - though a low-impedance response over a wide bandwidth does not in general come "for free".

Of course, in this case the simplest way to avoid the 100-MHz parallel resonance would be to omit the 50-pF capacitor, as it does not appear to provide any noticeable benefit when its series resonance is as low as 100-MHz.

chin wong

What are we getting at here? As design people know, RF design board is quite different from regular multi layers mixed signal board. In additions, the layout is quite difference. The fr is about 3GHz, which is much higher than normal digital design. It would not have concerned for lower frequence stuff. There is a trick to minimize this issue with good RF layout.

John D.

Hi, George.

The resonant peak issue came to my attention in a real-world case of having trouble with a Xilinx FPGA. In this example, the highest self-resonant frequency capacitor is in the artwork itself and would not be possible to avoid that.

Clearly it is possible to design systems that work, but keeping an eye out for rail voltage bypass imepdance across the frequency spectrum of interest, possibly with the inclusion of damping element(s), would be prudent.

Carl Schwab

John this discussion here brings to mind the "Foster reactance theorem" that I was taught in 1949. The theorem was attributed to the telephone laboratories in 1922 and a fellow named Zobel. It postulated when you parallel connected series resonate OR series connected parallel resonate circuits, the impedance (or the inverse) would be a succession of alternating poles and zeros. Now in 1922 they hadn’t developed the concept of poles and zeros but they understood the principal.

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