We all know of the technique of paralleling capacitors of different capacitances to achieve wideband bypassing, but here is a look at a hazard of which to be aware.
Consider two layers of some circuit board, the following being sort of a typical case:
The impedance of this arrangement is scaled vertically as Log (1+x) so that if the impedance goes to near-zero, or at least gets to be very small, our graph doesn't go off the bottom of the page.
The impedance versus frequency plot looks pretty good over a wide frequency range, but there is one glitch of an unwanted resonance, an impedance peak, that occurs slightly below 100 MHz.
Now consider this!
Improving the 50 pF really makes a mess of the bypassing over a vairly wide range of frequencies.
The key point of all this is as follows.
If you have some array of N capacitors connected in parallel, each with a different self resonant frequency, there will be some particular frequency above the self resonances of capacitors 1 to N-1 where those capacitors will exhibit some equivalent inductance.
That last capacitor, call that capacitor N, will yield a parallel resonance with those other capacitors' composite inductance and there will be some frequency between the N-1 resonant frequency and capacitor N's own self resonant frequency where bypassing may not be sufficient.
In this case, the 0.1 µF capacitor N-1 resonates at 10 MHz while the 50 pF capacitor N resonates at 3 GHz. The unwanted resonance peak lies between those two frequencies, in this example, somewhere near 800 MHz.
There is no escape from this effect. Just check to be sure that your design's unwanted resonance doesn't occur at a frequency critical to your circuit(s) operation.