Some troublesome digital chips were not starting up properly if their +5 Vcc was applied with too slow a rise time. (Hey, sometimes things like this can happen, right?) The minimum required rise time for that +5 Vcc rail was determined to be 45 mSec.
This was a problem which later resolved by the chip vendor, but while the problem still existed, a circuit was needed to delay Vcc application to the troublesome chips until the power supply voltage had risen to a particular threshold value, and not before, and to then apply the already risen power supply voltage to the chips with a relatively fast rise-time as sketched here:
There are such requirements for certain voltage monitoring ICs which disqualified them from this service because there would be unpredictable chip behaviors below their respective minimum required Vcc values.
Still, as the poet Robert Burns once noted, the best laid plans of mice and men "aft gang aglay" and so it was with this plan. The input versus output behavior of this circuit was affected by the power supply's own exhibition of a transient downward glitch at the moment of MOSFET switching:
However, we got away with it because once the power supply had gotten its own output voltage up, its recovery time from that glitch was rapid enough to give us a suitably rapid dV/dT to the troublesome chips at the moment of chip power-on.
This is the +5 Vcc switching circuit:
The troublesome chips had been divided into four separate loads, all of which were switched on at the same time. At the current levels involved, it took four of the available switching MOSFETs to carry the required load currents.
Artwork layout for this circuit was as follows:
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