Bypass Capacitor Boobytrap - John Dunn, Consultant, Ambertec, P.E., P.C.

We all know of the technique of paralleling capacitors of different capacitances to achieve wideband bypassing, but here is a look at a hazard of which to be aware.

Consider two layers of some circuit board, the following being sort of a typical case:  

  

Next, let's allow that some 20 µF electrolytic capacitor and some 0.1 µF ceramic capacitor are paralleled as a bypass and that this pair is in parallel with a third capacitance arising from two layers of the circuit board:   

 

The impedance of this arrangement is scaled vertically as Log (1+x) so that if the impedance goes to near-zero, or at least gets to be very small, our graph doesn't go off the bottom of the page.

The impedance versus frequency plot looks pretty good over a wide frequency range, but there is one glitch of an unwanted resonance, an impedance peak, that occurs slightly below 100 MHz.

Now consider this!  

 

Improving the 50 pF really makes a mess of the bypassing over a vairly wide range of frequencies.

The key point of all this is as follows.

If you have some array of N capacitors connected in parallel, each with a different self resonant frequency, there will be some particular frequency above the self resonances of capacitors 1 to N-1 where those capacitors will exhibit some equivalent inductance.

That last capacitor, call that capacitor N, will yield a parallel resonance with those other capacitors' composite inductance and there will be some frequency between the N-1 resonant frequency and capacitor N's own self resonant frequency where bypassing may not be sufficient.

In this case, the 0.1 µF capacitor N-1 resonates at 10 MHz while the 50 pF capacitor N resonates at 3 GHz. The unwanted resonance peak lies between those two frequencies, in this example, somewhere near 800 MHz.

There is no escape from this effect. Just check to be sure that your design's unwanted resonance doesn't occur at a frequency critical to your circuit(s) operation.

 

Comments

[George Storm]

Agreed that there will in principle always be multiple resonances, but fortunately there are design techniques that can minimise the heights of the peaks - though a low-impedance response over a wide bandwidth does not in general come "for free".

Of course, in this case the simplest way to avoid the 100-MHz parallel resonance would be to omit the 50-pF capacitor, as it does not appear to provide any noticeable benefit when its series resonance is as low as 100-MHz.

[chin wong]

What are we getting at here? As design people know, RF design board is quite different from regular multi layers mixed signal board. In additions, the layout is quite difference. The fr is about 3GHz, which is much higher than normal digital design. It would not have concerned for lower frequence stuff. There is a trick to minimize this issue with good RF layout.

[John D.]

Hi, George.

The resonant peak issue came to my attention in a real-world case of having trouble with a Xilinx FPGA. In this example, the highest self-resonant frequency capacitor is in the artwork itself and would not be possible to avoid that.

Clearly it is possible to design systems that work, but keeping an eye out for rail voltage bypass imepdance across the frequency spectrum of interest, possibly with the inclusion of damping element(s), would be prudent.

[Carl Schwab]

John this discussion here brings to mind the "Foster reactance theorem" that I was taught in 1949. The theorem was attributed to the telephone laboratories in 1922 and a fellow named Zobel. It postulated when you parallel connected series resonate OR series connected parallel resonate circuits, the impedance (or the inverse) would be a succession of alternating poles and zeros. Now in 1922 they hadn’t developed the concept of poles and zeros but they understood the principal.